[VP] Remove VP_PROPERTY_REDUCTION and VP_PROPERTY_CMP [nfc] #105551
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These lists are quite static and several of the parameters are actually constant across all users. Heavy use of macros is undesirable, and not idiomatic in LLVM, so let's just use the niave switch cases. I'll probably continue with removing the other property macros. These two just happened to be the two I actually had to figure out for an unrelated change.
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@llvm/pr-subscribers-llvm-ir @llvm/pr-subscribers-llvm-selectiondag Author: Philip Reames (preames) ChangesThese lists are quite static and several of the parameters are actually constant across all users. Heavy use of macros is undesirable, and not idiomatic in LLVM, so let's just use the naive switch cases. I'll probably continue with removing the other property macros. These two just happened to be the two I actually had to figure out for an unrelated change. Full diff: https://github.com/llvm/llvm-project/pull/105551.diff 3 Files Affected:
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index a4a1000d37259e..3ff74758bc80ce 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -129,11 +129,6 @@
#define VP_PROPERTY_MEMOP(POINTERPOS, DATAPOS)
#endif
-// Map this VP reduction intrinsic to its reduction operand positions.
-#ifndef VP_PROPERTY_REDUCTION
-#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS)
-#endif
-
// A property to infer VP binary-op SDNode opcodes automatically.
#ifndef VP_PROPERTY_BINARYOP
#define VP_PROPERTY_BINARYOP
@@ -144,13 +139,6 @@
#define VP_PROPERTY_CASTOP
#endif
-// This VP Intrinsic is a comparison operation
-// The condition code arg is at CCPOS and accepts floating-point condition
-// codes if ISFP is set, else it accepts integer condition codes.
-#ifndef VP_PROPERTY_CMP
-#define VP_PROPERTY_CMP(CCPOS, ISFP)
-#endif
-
/// } Property Macros
///// Integer Arithmetic {
@@ -567,7 +555,6 @@ END_REGISTER_VP_SDNODE(VP_SETCC)
BEGIN_REGISTER_VP_INTRINSIC(vp_fcmp, 3, 4)
HELPER_MAP_VPID_TO_VPSD(vp_fcmp, VP_SETCC)
VP_PROPERTY_FUNCTIONAL_OPC(FCmp)
-VP_PROPERTY_CMP(2, true)
VP_PROPERTY_CONSTRAINEDFP(0, 1, experimental_constrained_fcmp)
END_REGISTER_VP_INTRINSIC(vp_fcmp)
@@ -575,7 +562,6 @@ END_REGISTER_VP_INTRINSIC(vp_fcmp)
BEGIN_REGISTER_VP_INTRINSIC(vp_icmp, 3, 4)
HELPER_MAP_VPID_TO_VPSD(vp_icmp, VP_SETCC)
VP_PROPERTY_FUNCTIONAL_OPC(ICmp)
-VP_PROPERTY_CMP(2, false)
END_REGISTER_VP_INTRINSIC(vp_icmp)
///// } Comparisons
@@ -654,7 +640,6 @@ END_REGISTER_VP(vp_gather, VP_GATHER)
#define HELPER_REGISTER_REDUCTION_VP(VPID, VPSD, INTRIN) \
BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, 1) \
VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
- VP_PROPERTY_REDUCTION(0, 1) \
END_REGISTER_VP(VPID, VPSD)
// llvm.vp.reduce.add(start,x,mask,vlen)
@@ -724,11 +709,9 @@ HELPER_REGISTER_REDUCTION_VP(vp_reduce_fminimum, VP_REDUCE_FMINIMUM,
#define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, INTRIN) \
BEGIN_REGISTER_VP_INTRINSIC(VPID, 2, 3) \
BEGIN_REGISTER_VP_SDNODE(VPSD, 1, VPID, 2, 3) \
- VP_PROPERTY_REDUCTION(0, 1) \
END_REGISTER_VP_SDNODE(VPSD) \
BEGIN_REGISTER_VP_SDNODE(SEQ_VPSD, 1, VPID, 2, 3) \
HELPER_MAP_VPID_TO_VPSD(VPID, SEQ_VPSD) \
- VP_PROPERTY_REDUCTION(0, 1) \
END_REGISTER_VP_SDNODE(SEQ_VPSD) \
VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
END_REGISTER_VP_INTRINSIC(VPID)
@@ -793,11 +776,9 @@ END_REGISTER_VP(experimental_vp_splat, EXPERIMENTAL_VP_SPLAT)
#undef HELPER_MAP_VPID_TO_VPSD
#undef VP_PROPERTY_BINARYOP
#undef VP_PROPERTY_CASTOP
-#undef VP_PROPERTY_CMP
#undef VP_PROPERTY_CONSTRAINEDFP
#undef VP_PROPERTY_FUNCTIONAL_INTRINSIC
#undef VP_PROPERTY_FUNCTIONAL_OPC
#undef VP_PROPERTY_FUNCTIONAL_SDOPC
#undef VP_PROPERTY_NO_FUNCTIONAL
#undef VP_PROPERTY_MEMOP
-#undef VP_PROPERTY_REDUCTION
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 18a3b7bce104a7..ba388625f6589f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -503,13 +503,26 @@ bool ISD::isVPBinaryOp(unsigned Opcode) {
bool ISD::isVPReduction(unsigned Opcode) {
switch (Opcode) {
default:
- break;
-#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
-#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
-#define END_REGISTER_VP_SDNODE(VPSD) break;
-#include "llvm/IR/VPIntrinsics.def"
+ return false;
+ case ISD::VP_REDUCE_ADD:
+ case ISD::VP_REDUCE_MUL:
+ case ISD::VP_REDUCE_AND:
+ case ISD::VP_REDUCE_OR:
+ case ISD::VP_REDUCE_XOR:
+ case ISD::VP_REDUCE_SMAX:
+ case ISD::VP_REDUCE_SMIN:
+ case ISD::VP_REDUCE_UMAX:
+ case ISD::VP_REDUCE_UMIN:
+ case ISD::VP_REDUCE_FMAX:
+ case ISD::VP_REDUCE_FMIN:
+ case ISD::VP_REDUCE_FMAXIMUM:
+ case ISD::VP_REDUCE_FMINIMUM:
+ case ISD::VP_REDUCE_FADD:
+ case ISD::VP_REDUCE_FMUL:
+ case ISD::VP_REDUCE_SEQ_FADD:
+ case ISD::VP_REDUCE_SEQ_FMUL:
+ return true;
}
- return false;
}
/// The operand position of the vector mask.
diff --git a/llvm/lib/IR/IntrinsicInst.cpp b/llvm/lib/IR/IntrinsicInst.cpp
index db3b0196f66fd6..092c375dcc5b9c 100644
--- a/llvm/lib/IR/IntrinsicInst.cpp
+++ b/llvm/lib/IR/IntrinsicInst.cpp
@@ -728,14 +728,25 @@ Function *VPIntrinsic::getDeclarationForParams(Module *M, Intrinsic::ID VPID,
bool VPReductionIntrinsic::isVPReduction(Intrinsic::ID ID) {
switch (ID) {
+ case Intrinsic::vp_reduce_add:
+ case Intrinsic::vp_reduce_mul:
+ case Intrinsic::vp_reduce_and:
+ case Intrinsic::vp_reduce_or:
+ case Intrinsic::vp_reduce_xor:
+ case Intrinsic::vp_reduce_smax:
+ case Intrinsic::vp_reduce_smin:
+ case Intrinsic::vp_reduce_umax:
+ case Intrinsic::vp_reduce_umin:
+ case Intrinsic::vp_reduce_fmax:
+ case Intrinsic::vp_reduce_fmin:
+ case Intrinsic::vp_reduce_fmaximum:
+ case Intrinsic::vp_reduce_fminimum:
+ case Intrinsic::vp_reduce_fadd:
+ case Intrinsic::vp_reduce_fmul:
+ return true;
default:
- break;
-#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
-#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
-#define END_REGISTER_VP_INTRINSIC(VPID) break;
-#include "llvm/IR/VPIntrinsics.def"
+ return false;
}
- return false;
}
bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) {
@@ -753,13 +764,11 @@ bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) {
bool VPCmpIntrinsic::isVPCmp(Intrinsic::ID ID) {
switch (ID) {
default:
- break;
-#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
-#define VP_PROPERTY_CMP(CCPOS, ...) return true;
-#define END_REGISTER_VP_INTRINSIC(VPID) break;
-#include "llvm/IR/VPIntrinsics.def"
+ return false;
+ case Intrinsic::vp_fcmp:
+ case Intrinsic::vp_icmp:
+ return true;
}
- return false;
}
bool VPBinOpIntrinsic::isVPBinOp(Intrinsic::ID ID) {
@@ -793,22 +802,10 @@ static ICmpInst::Predicate getIntPredicateFromMD(const Value *Op) {
}
CmpInst::Predicate VPCmpIntrinsic::getPredicate() const {
- bool IsFP = true;
- std::optional<unsigned> CCArgIdx;
- switch (getIntrinsicID()) {
- default:
- break;
-#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
-#define VP_PROPERTY_CMP(CCPOS, ISFP) \
- CCArgIdx = CCPOS; \
- IsFP = ISFP; \
- break;
-#define END_REGISTER_VP_INTRINSIC(VPID) break;
-#include "llvm/IR/VPIntrinsics.def"
- }
- assert(CCArgIdx && "Unexpected vector-predicated comparison");
- return IsFP ? getFPPredicateFromMD(getArgOperand(*CCArgIdx))
- : getIntPredicateFromMD(getArgOperand(*CCArgIdx));
+ assert(isVPCmp(getIntrinsicID()));
+ return getIntrinsicID() == Intrinsic::vp_fcmp
+ ? getFPPredicateFromMD(getArgOperand(2))
+ : getIntPredicateFromMD(getArgOperand(2));
}
unsigned VPReductionIntrinsic::getVectorParamPos() const {
@@ -821,27 +818,15 @@ unsigned VPReductionIntrinsic::getStartParamPos() const {
std::optional<unsigned>
VPReductionIntrinsic::getVectorParamPos(Intrinsic::ID ID) {
- switch (ID) {
-#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
-#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) return VECTORPOS;
-#define END_REGISTER_VP_INTRINSIC(VPID) break;
-#include "llvm/IR/VPIntrinsics.def"
- default:
- break;
- }
+ if (isVPReduction(ID))
+ return 1;
return std::nullopt;
}
std::optional<unsigned>
VPReductionIntrinsic::getStartParamPos(Intrinsic::ID ID) {
- switch (ID) {
-#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
-#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) return STARTPOS;
-#define END_REGISTER_VP_INTRINSIC(VPID) break;
-#include "llvm/IR/VPIntrinsics.def"
- default:
- break;
- }
+ if (isVPReduction(ID))
+ return 0;
return std::nullopt;
}
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preames
added a commit
to preames/llvm-project
that referenced
this pull request
Aug 21, 2024
These lists are quite static. Heavy use of macros is undesirable, and not idiomatic in LLVM, so let's just use the naive switch cases. Note that the first two fields in the CONSTRAINEDFP property were utterly unused (aside from a C++ test). In the same vien as llvm#105551. Once both changes have landed, we'll be left with _BINARYOP which needs a bit of additional untangling, and the actual opcode mappings.
lukel97
approved these changes
Aug 29, 2024
preames
added a commit
that referenced
this pull request
Aug 29, 2024
#105574) These lists are quite static. Heavy use of macros is undesirable, and not idiomatic in LLVM, so let's just use the naive switch cases. Note that the first two fields in the CONSTRAINEDFP property were utterly unused (aside from a C++ test). In the same vien as #105551. Once both changes have landed, we'll be left with _BINARYOP which needs a bit of additional untangling, and the actual opcode mappings.
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These lists are quite static and several of the parameters are actually constant across all users. Heavy use of macros is undesirable, and not idiomatic in LLVM, so let's just use the naive switch cases.
I'll probably continue with removing the other property macros. These two just happened to be the two I actually had to figure out for an unrelated change.